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Beyond Design: FPGA PCB Design Challenges
The primary issue is generating optimal FPGA pin assignments that do not add vias and signal layers to a PCB stackup or increase the time required to integrate the FPGA with the PCB. Engineers generally do not consider FPGA pin assignments that expedite the PCB layout. Hundreds of logical signals need to be mapped to the physical pin-out of the device, and they must also harmonize with the routing requirements whilst maintaining the electrical integrity of the design.















  

PCB Designers Notebook: Embedding Components, Part 2
Technology and processes for embedding capacitor and inductor elements rely on several unique methodologies. Regarding providing capacitor functions, IPC-4821 defines two methodologies for forming capacitor elements within the PCB structure: laminate based (copper-dielectric-copper) or planar process and non-laminate process using deposited dielectric materials.

Become a PCB Certified Designer! Finding a class to fit your busy schedule has never been easier. More Classes, More Dates, More Times. Powered Only by EPTAC. Learn more now.

 

It’s Only Common Sense: Finally, the DoD Gets It!
Last week a friend of mine sent me this excerpt from the Congressional Record. Yes, that congressional record. If this doesn’t set your hair on fire, then nothing will.

  


ECWC 14 Wrap-Up with Tim Lee and Happy Holden
Minsu (Tim) Lee is the secretariat of the ECWC 14 Worldwide Printed Circuit Conference, which recently concluded in Seoul, South Korea. Tim is also the program manager of the Korean Printed Circuit Assoc. We had a few minutes together after the conference ended to review the week’s events and the Korean PCB industry. Tim also focused on the ongoing situation with North Korea, which resulted in many Chinese paper contributors being denied visas for ECWC 14.

 

Design News & Additional Information


SMTA International Technical Program Expands, Includes Research from HDPUG and AREA Consortium
SMTA announces an expanded program for the final day of the SMTA International Conference, September 17 - 21, 2017 in Rosemont, Illinois. In addition to the Lead-Free Symposium, the technical committee expanded the Thursday program to four concurrent tracks. The three additional tracks will focus on Advanced Packaging Technology, Manufacturing Excellence, and Inspection Technologies.


Cadence Reports Revenue of $479 Million in Q2 2017
Cadence reported second quarter 2017 revenue of $479 million, compared to revenue of $453 million reported for the same period in 2016. On a GAAP basis, Cadence recognized net income of $69 million, or $0.25 per share on a diluted basis, in the second quarter of 2017, compared to net income of $49 million, or $0.17 per share on a diluted basis, for the same period in 2016.


Zuken Unveils XJTAG DFT Assistant for CR-8000 PCB Design Suite
Zuken and XJTAG have entered into a partnership to enhance Zuken’s CR-8000 with a design for test (DFT) capability that will improve test coverage during schematic entry. The capability is based on XJTAG’s DFT Assistant, and will be available later this year as a free plugin for Zuken’s CR-8000 Design Gateway users.


EDI CON USA 2017 Adds Short Courses
The Electronic Design Innovation Conference and Exhibition (EDI CON) USA, the first industry event to bring together RF/microwave and high-speed digital design engineers and system integrators, has added a full day of training to its conference program at the Hynes Convention Center, September 11-13 in Boston, Massachusetts.

For all the latest Printed Circuit Board Design news and information, go to PCBDesign007 right now!



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