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 Beyond Design: FPGA PCB Design Challenges The primary issue is generating optimal FPGA pin assignments that do not add vias and signal layers to a PCB stackup or increase the time required to integrate the FPGA with the PCB. Engineers generally do not consider FPGA pin assignments that expedite the PCB layout. Hundreds of logical signals need to be mapped to the physical pin-out of the device, and they must also harmonize with the routing requirements whilst maintaining the electrical integrity of the design. |
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 PCB Designers Notebook: Embedding Components, Part 2 Technology and processes for embedding capacitor and inductor elements rely on several unique methodologies. Regarding providing capacitor functions, IPC-4821 defines two methodologies for forming capacitor elements within the PCB structure: laminate based (copper-dielectric-copper) or planar process and non-laminate process using deposited dielectric materials. |
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 It’s Only Common Sense: Finally, the DoD Gets It! Last week a friend of mine sent me this excerpt from the Congressional Record. Yes, that congressional record. If this doesn’t set your hair on fire, then nothing will. |
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 ECWC 14 Wrap-Up with Tim Lee and Happy Holden Minsu (Tim) Lee is the secretariat of the ECWC 14 Worldwide Printed Circuit Conference, which recently concluded in Seoul, South Korea. Tim is also the program manager of the Korean Printed Circuit Assoc. We had a few minutes together after the conference ended to review the week’s events and the Korean PCB industry. Tim also focused on the ongoing situation with North Korea, which resulted in many Chinese paper contributors being denied visas for ECWC 14. |
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